A3R12E30DBF A3R12E40DBF 512Mb DDRII DRAM IC力积电子-【深圳市佳源伟业电子有限公司】电子元器件代理商和电子产品厂商

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ZILLTEK

ZILLTEK钰太科技成立于2005年12月12日台湾新竹，是一家专业模拟及混合讯号IC设计公司。成立至今积极投注研发资源、快速开发新产品。

钰太科技的产品线包含了从触控屏幕控制IC，电源管理IC（A. DC / DC转换; B. AC / DC转换），白光LED驱动器及MEMS Microphone sensor等，主要用于消费产品的应用，如无线宽带，数据通信（AP路由器，IAD，GPON等USB 3.0应用程序（Pen Driver，SSD，硬盘等），液晶电视 /显示器，机顶盒，监视（CCTV，IP CAM，婴儿监视器等），平板计算机，MID，PDA，DVD播放器，IA, Smart phone, NoteBook产品等。

A3R12E30DBF A3R12E40DBF 512Mb DDRII DRAM IC ZENTEL

ZENTEL DRAM IC
512Mb

64Mx8

1.8V

DDR2-800/1066

FBGA-60

A3R12E30DBF A3R12E40DBF 512Mb DDRII DRAM IC ZENTEL

Features :

• Double-data-rate architecture; two data transfers per clock

cycle

• The high-speed data transfer is realized by the 4 bits

prefect pipelined architecture

• Bi-directional differential data strobe (DQS and /DQS) is

transmitted/received with data for capturing data at the

receiver

• DQS is edge-aligned with data for READs; centeraligned

with data for WRITEs

• Differential clock inputs (CK and /CK)

• DLL aligns DQ and DQS transitions with CK

transitions

• Commands entered on each positive CK edge; data and

data mask referenced to both edges of DQS

• Data mask (DM) for write data

• Posted /CAS by programmable additive latency for

better command and data bus efficiency

• On-Die-Termination for better signal quality

• Programmable RDQS, /RDQS output for making × 8

organization compatible to × 4 organization

• /DQS, (/RDQS) can be disabled for single-ended

Data Strobe operation

• Off-Chip Driver (OCD) impedance adjustment is not supported

Specifications:

• Density: 512 bits

• Organization

− 16M words × 8 bits × 4 banks (A3R12E30DBF)

− 8M words × 16 bits × 4 banks (A3R12E40DBF)

• Package

− 60-ball FBGA(μBGA) (A3R12E30DBF)

− 84-ball FBGA(μBGA) (A3R12E40DBF)

− Lead-free (RoHS compliant)

• Power supply: VDD, VDDQ = 1.8V ± 0.1V

• Data rate: 1066Mbps/800Mbps (max.)

• 1KB page size (A3R12E30DBF)

− Row address: A0 to A13

− Column address: A0 to A9

• 2KB page size (A3R12E40DBF)

− Row address: A0 to A12

− Column address: A0 to A9

• Four internal banks for concurrent operation

• Interface: SSTL_18

• Burst lengths (BL): 4, 8

• Burst type (BT):

− Sequential (4, 8)

− Interleave (4, 8)

• /CAS Latency (CL): 3, 4, 5, 6, 7

• Precharge: auto Precharge option for each burst

access

• Driver strength: normal/weak

• Low self-refresh current parts are available (8EPH)

• Refresh: auto-refresh, self-refresh

• Refresh cycles: 8192 cycles/64ms

− Average refresh period

7.8μs at TC≦ +85°C

3.9μs at TC＞ +85°C

• Industrial grade compliant with AEC-Q100 grade3

• Automotive grade compliant with AEC-Q100 grade2

• Operating case temperature range

− TC = 0°C to +85°C (Commercial grade)*

− TC = -40°C to +95°C (Industrial grade)*

− TC = -40°C to +105°C (Automotive grade)*

A3R12E30DBF A3R12E40DBF 512Mb DDRII Synchronous DRAM IC ZENTEL