A3S64D40GTP A3S56D40GTP ZENTEL DDR1 SDRAM
FEATURES
-VDD=VDDQ=2.5V+0.2V
- Operating Temperature:
Commercial: 0 ~ 70℃
Industrial : -40 ~ 85℃
- Double data rate architecture ; two data transfers per clock cycle.
- Bidirectional , data strobe (DQS) is transmitted/received with data
- Differential clock input (CLK and /CLK)
- DLL aligns DQ and DQS transitions with CLK transitions edges of DQS
- Commands entered on each positive CLK edge ;
- Data and data mask referenced to both edges of DQS
- 4 bank operation controlled by BA0 , BA1 (Bank Address)
- CAS latency 2 / 2.5 / 3 (programmable) ;
- Burst length 2 / 4 / 8 (programmable)
- Burst type: Sequential / Interleave (programmable)
- Auto Precharge / All Bank Precharge controlled by A10
- Support concurrent Auto Precharge
- 4096 refresh cycles / 64ms (4 banks concurrent refresh)
- Auto Refresh and Self Refresh
- Row address A0-11 / Column address A0-8
- SSTL_2 Interface
- Package 400-mil, 66-pin Thin Small Outline Package (TSOP II) with 0.65mm lead pitch
A3S64D40GTP A3S56D40GTP ZENTEL DDR1 SDRAM