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ZILLTEK钰太科技成立于2005年12月12日台湾新竹，是一家专业模拟及混合讯号IC设计公司。成立至今积极投注研发资源、快速开发新产品。
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A3V28S40JTP Zentel Automotive DRAM IC
General Description
A3V28S40JTP is organized as 4-bank x 2,097,
154-word x 16-bit Synchronous DRAM with LVTTL interface. 
All inputs and outputs are referenced to the rising edge of CLK. 
A3V28S40JTP achieve very high speed data rates up to 166MHz, 
and are suitable for main memories
or graphic memories in computer systems
A3V28S40JTP Zentel 128M Single Data Rate Synchronous DRAM IC

Features
- Single 3.3V ±0.3V power supply
- Maximum clock frequency:
- 60:166MHz<3-3-3>/-70:143MHz<3-3-3>/-75:133MHz<3-3-3>
- Fully synchronous operation referenced to clock rising edge
- 4-bank operation controlled by BA0, BA1 (Bank Address)
- /CAS latency- 2/3 (programmable)
- Burst length- 1/2/4/8/FP (programmable)
- Burst type- Sequential and interleave burst (programmable)
- Byte Control- LDQM and UDQM (A3V28S40JTP)
- Random column access
- Auto precharge / All bank precharge controlled by A10
- Support concurrent auto-precharge
- Auto and self refresh
- 4096 refresh cycles /64ms
- Temperature range: -40℃ to +85℃
- LVTTL Interface
- Package
400-mil, 54-pin Thin Small Outline (TSOP II) with 0.8mm lead pitch

A3V28S40JTP Zentel 128M Single Data Rate Synchronous DRAM IC Photo:



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