ZILLTEK Technology was established in 2005 in Taiwan.ZILLTEK is a professional analog and mixed signal IC design company. Since its establishment, it has been actively betting on R&D resources and rapidly developing new products.
ZILLTEK  product line includes touch screen control ICs, power management ICs (A/DC/DC conversion, B. AC/DC conversion), white LED drivers and MEMS Microphone sensors, etc., which are mainly used for consumer products. Such as wireless broadband, data communication (AP routers, IAD, GPON, etc.) USB 3.0 applications (Pen-Driver, SSD, hard disk, etc.), LCD TVs, monitors, set-top boxes, surveillance (CCTV, IP-CAM, baby monitors, etc.) , tablet, MID, PDA, DVD player, IA, Smart phone, NoteBook products, etc.

A3R12E30DBF A3R12E40DBF 512Mb DDRII Synchronous DRAM IC ZENTEL
A3R12E30DBF A3R12E40DBF 512Mb DDRII Synchronous DRAM IC ZENTEL

Features :
• Double-data-rate architecture; two data transfers per clock
• The high-speed data transfer is realized by the 4 bits
prefect pipelined architecture
• Bi-directional differential data strobe (DQS and /DQS) is
transmitted/received with data for capturing data at the
• DQS is edge-aligned with data for READs; centeraligned
with data for WRITEs
• Differential clock inputs (CK and /CK)
• DLL aligns DQ and DQS transitions with CK
• Commands entered on each positive CK edge; data and
data mask referenced to both edges of DQS
• Data mask (DM) for write data
• Posted /CAS by programmable additive latency for
better command and data bus efficiency
• On-Die-Termination for better signal quality
• Programmable RDQS, /RDQS output for making × 8
organization compatible to × 4 organization
• /DQS, (/RDQS) can be disabled for single-ended
Data Strobe operation
• Off-Chip Driver (OCD) impedance adjustment is not  supported 
• Density: 512 bits
• Organization
− 16M words × 8 bits × 4 banks (A3R12E30DBF)
− 8M words × 16 bits × 4 banks (A3R12E40DBF)
• Package
− 60-ball FBGA(μBGA) (A3R12E30DBF)
− 84-ball FBGA(μBGA) (A3R12E40DBF)
− Lead-free (RoHS compliant)
• Power supply: VDD, VDDQ = 1.8V ± 0.1V
• Data rate: 1066Mbps/800Mbps (max.)
• 1KB page size (A3R12E30DBF)
− Row address: A0 to A13
− Column address: A0 to A9
• 2KB page size (A3R12E40DBF)
− Row address: A0 to A12
− Column address: A0 to A9
• Four internal banks for concurrent operation
• Interface: SSTL_18
• Burst lengths (BL): 4, 8
• Burst type (BT):
− Sequential (4, 8)
− Interleave (4, 8)
• /CAS Latency (CL): 3, 4, 5, 6, 7
• Precharge: auto Precharge option for each burst
• Driver strength: normal/weak
• Low self-refresh current parts are available (8EPH)
• Refresh: auto-refresh, self-refresh
• Refresh cycles: 8192 cycles/64ms
− Average refresh period
7.8μs at TC≦ +85°C
3.9μs at TC> +85°C
• Industrial grade compliant with AEC-Q100 grade3
• Automotive grade compliant with AEC-Q100 grade2
• Operating case temperature range
− TC = 0°C to +85°C (Commercial grade)*
− TC = -40°C to +95°C (Industrial grade)*
− TC = -40°C to +105°C (Automotive grade)* 

A3R12E30DBF A3R12E40DBF 512Mb DDRII Synchronous DRAM IC ZENTEL
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